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TJA1021
LIN 2.0/SAE J2602 transceiver
Rev. 01 -- 16 October 2006 Objective data sheet
1. General description
The TJA1021 is the interface between the Local Interconnect Network (LIN) master/slave protocol controller and the physical bus in a LIN. It is primarily intended for in-vehicle sub-networks using baud rates from 1 kBd up to 20 kBd and is LIN 2.0/SAE J2602 compliant. The TJA1021 is pin-to-pin compatible with the TJA1020 and improved on ElectroStatic Discharge (ESD). The transmit data stream of the protocol controller at the transmit data input (TXD) is converted by the TJA1021 into a bus signal with optimized slew rate and wave shaping to minimize ElectroMagnetic Emission (EME). The LIN bus output pin is pulled HIGH via an internal termination resistor. For a master application an external resistor in series with a diode should be connected between pin INH or pin VBAT and pin LIN. The receiver detects the data stream at the LIN bus input pin and transfers it via pin RXD to the microcontroller. In sleep mode the power consumption of the TJA1021 is very low, whereas in failure modes the power consumption is reduced to a minimum.
2. Features
2.1 General
I I I I I I I I I I LIN 2.0/SAE J2602 compliant Baud rate up to 20 kBd Very low ElectroMagnetic Emission (EME) High ElectroMagnetic Immunity (EMI) Passive behavior in unpowered state Input levels compatible with 3.3 V and 5 V devices Integrated termination resistor for LIN slave applications Wake-up source recognition (local or remote) Supports K-line like functions Pin-to-pin compatible with TJA1020
2.2 Low power management
I Very low current consumption in sleep mode with local and remote wake-up
2.3 Protections
I High ESD robustness: 6 kV according to IEC 61000-4-2 for pins LIN, VBAT and WAKE_N I Transmit data (TXD) dominant time-out function
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TJA1021
LIN 2.0/SAE J2602 transceiver
I Bus terminal and battery pin protected against transients in the automotive environment (ISO 7637) I Bus terminal short-circuit proof to battery and ground I Thermally protected
3. Quick reference data
Table 1. Quick reference data VBAT = 5.5 V to 27 V; Tvj = -40 C to +150 C; RL(LIN-VBAT) = 500 ; all voltages are defined with respect to ground; positive currents flow into the IC; typical values are given at VBAT = 12 V; unless otherwise specified.[1] Symbol VBAT IBAT Parameter supply voltage on pin VBAT supply current on pin VBAT Conditions operating mode sleep mode standby mode; bus recessive normal mode; bus recessive normal mode; bus dominant VLIN voltage on pin LIN with respect to GND, VBAT and VWAKE_N Min 5.5 4 150 0.4 1 -40 Typ 12 7 450 0.8 2 Max 27 10 1000 2 6 +40 Unit V A A mA mA V
Tvj
[1]
virtual junction temperature
-40
-
+150
C
All parameters are guaranteed over the virtual junction temperature range by design. Products are 100 % tested at 125 C ambient temperature on wafer level (pre-testing). Cased products are 100 % tested at 25 C ambient temperature (final testing). Both pre-testing and final testing use correlated test conditions to cover the specified temperature and power supply voltage range.
4. Ordering information
Table 2. Ordering information Package Name TJA1021T/10; TJA1021T/20 TJA1021U/10; TJA1021U/20
[1]
Type number[1]
Description plastic small outline package; 8 leads; body width 3.9 mm bare die; die dimensions:
Version SOT96-1 -
SO8 -
TJA1021T/20, TJA1021U/20: for the version which supports baud rates up to 20 kBd; TJA1021T/10, TJA1021U/10: for the version which supports baud rates up to 10.4 kBd (SAE J2602).
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TJA1021
LIN 2.0/SAE J2602 transceiver
5. Block diagram
VBAT
7 WAKE-UP TIMER CONTROL 8 INH
WAKE_N
3
SLP_N
2
SLEEP/ NORMAL TIMER
TEMPERATURE PROTECTION 6 LIN
TXD
4
TXD TIME-OUT TIMER
TJA1021
1 RXD/ INT BUS TIMER FILTER 5 GND
RXD
001aae066
Fig 1. Block diagram
6. Pinning information
6.1 Pinning
RXD SLP_N WAKE_N TXD
1 2
8 7
INH VBAT LIN GND
TJA1021T
3 4
001aae067
6 5
Fig 2. Pin configuration TJA1021T
Fig 3. Bonding pad locations ()
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TJA1021
LIN 2.0/SAE J2602 transceiver
6.2 Pin description
Table 3. Symbol RXD SLP_N WAKE_N TXD GND LIN VBAT INH Pin description Pin 1 2 3 4 5 6 7 8 Description receive data output (open-drain); active LOW after a wake-up event sleep control input (active LOW); controls inhibit output; resets wake-up source flag on TXD and wake-up request on RXD local wake-up input (active LOW); negative edge triggered transmit data input; active LOW output after a local wake-up event ground LIN bus line input/output battery supply battery related inhibit output for controlling an external voltage regulator; active HIGH after a wake-up event
Table 4. Symbol RXD SLP_N
Bonding pad description Pad 1 2 X[1] Y[1] Description receive data output (open-drain); active LOW after a wake-up event sleep control input (active LOW); controls inhibit output; resets wake-up source flag on TXD and wake-up request on RXD local wake-up input (active LOW); negative edge triggered transmit data input; active LOW output after a local wake-up event ground LIN bus line input/output battery supply battery related inhibit output for controlling an external voltage regulator; active HIGH after a wake-up event
WAKE_N TXD GND LIN VBAT INH
3 4 5 6 7 8

[1]
All coordinates (m) represent the position of the center of each pad with respect to the bottom left-hand corner of the top aluminium layer (see Figure 3).
7. Functional description
The TJA1021 is the interface between the LIN master/slave protocol controller and the physical bus in a Local Interconnect Network (LIN). The TJA1021 is LIN 2.0/SAE J2602 compliant and provides optimum ElectroMagnetic Compatibility (EMC) performance due to wave shaping of the LIN output. The /20 version of the TJA1021 is optimized for the maximum specified LIN transmission speed of 20 kBd; the /10 version of the TJA1021 is optimized for the LIN transmission speed of 10.4 kBd as specified by the SAE J2602.
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TJA1021
LIN 2.0/SAE J2602 transceiver
7.1 Operating modes
The TJA1021 provides a mode of normal operation, an intermediate mode, a Power-up mode and a very-low-power mode. Figure 4 shows the state diagram.
Power-on
INH: high TERM. = 30 k RXD: floating TXD: weak pull-down Transmitter: off
t(SLP_N = 1) > tgotonorm
Normal
INH: high TERM. = 30 k RXD: receive data output TXD: transmit data input Transmitter: on
switching on VBAT
t(SLP_N = 1) > tgotonorm
t(SLP_N = 1) > tgotonorm t(SLP_N = 0) > tgotosleep
Sleep
INH: floating TERM. = high ohmic RXD: floating TXD: weak pull-down Transmitter: off t(WAKE_N = 0; after 10) > tWAKE_N or t(LIN = 01; after LIN = 0) > tBUS
Standby
INH: high TERM. = 30 k RXD: low TXD: wake source output Transmitter: off
001aae073
TERM.: slave termination resistor, connected between pins LIN and VBAT.
Fig 4. State diagram Table 5. Mode Sleep Standby[1] Operating modes SLP_N 0 0 TXD (output) weak pull-down RXD floating INH floating HIGH Transmitter off off Remarks no wake-up request detected wake-up request detected; in this mode the microcontroller can read the wake-up source: remote or local wake-up
[2][3][4]
weak pull-down if LOW[3] remote wake-up; strong pull-down if local wake-up[2] HIGH: recessive state LOW: dominant state weak pull-down
Normal mode
1
HIGH: recessive state HIGH LOW: dominant state
normal mode
Power-on mode 0
floating
HIGH
off
[5]
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TJA1021
LIN 2.0/SAE J2602 transceiver
[1] [2] [3] [4] [5]
The standby mode is entered automatically upon any local or remote wake-up event during sleep mode. Pin INH and the 30 k termination resistor at pin LIN are switched on. The internal wake-up source flag (set if a local wake-up did occur and fed to pin TXD) will be reset when entering normal mode (SLP_N goes HIGH). The wake-up interrupt (on pin RXD) is released when entering normal mode (SLP_N goes HIGH). The normal mode is entered during a positive edge on SLP_N. As long as TXD is LOW, the transmitter is off. In the event of a short-circuit to ground on pin TXD, the transmitter will be disabled. The power-on mode is entered after switching on VBAT.
7.2 Sleep mode
This mode is the most power saving mode of the TJA1021. Despite its extreme low current consumption, the TJA1021 can still be waken up remotely via pin LIN, or waken up locally via pin WAKE_N, or activated directly via pin SLP_N. Filters at the inputs of the receiver (LIN), of pin WAKE_N and of pin SLP_N are preventing unwanted wake-up events due to automotive transients or EMI. All wake-up events have to be maintained for a certain time period (tdom(LIN), twake(dom)WAKE_N and tgotonorm). The sleep mode is initiated by a falling edge on the pin SLP_N in normal mode. To enter the sleep mode successfully (INH becomes floating), the sleep command (pin SLP_N = LOW) must be maintained for at least tgotosleep. In sleep mode the internal slave termination between pins LIN and VBAT is disabled to minimize the power dissipation in case pin LIN is short-circuited to ground. Only a weak pull-up between pins LIN and VBAT is present. The sleep mode can be activated independently from the actual level on pin LIN, pin TXD or pin WAKE_N. So it is guaranteed that the lowest power consumption is achievable even in case of a continuous dominant level on pin LIN or a continuous LOW on pin WAKE_N. When VBAT drops below the power-on-reset threshold Vth(POR)L, the TJA1021 enters sleep mode.
7.3 Standby mode
The standby mode is entered automatically whenever a local or remote wake-up occurs while the TJA1021 is in its sleep mode. These wake-up events activate pin INH and enable the slave termination resistor at the pin LIN. As a result of the HIGH condition on pin INH the voltage regulator and the microcontroller can be activated. The standby mode is signalled by a LOW-level on pin RXD which can be used as an interrupt for the microcontroller. In the standby mode (pin SLP_N is still LOW), the condition of pin TXD (weak pull-down or strong pull-down) indicates the wake-up source: weak pull-down for a remote wake-up request and strong pull-down for a local wake-up request. Setting pin SLP_N HIGH during standby mode results in the following events:
* An immediate reset of the wake-up source flag; thus releasing the possible strong
pull-down at pin TXD before the actual mode change (after tgotonorm) is performed
* A change into normal mode if the HIGH level on pin SLP_N has been maintained for a
certain time period (tgotonorm) while pin TXD is pulled HIGH
* An immediate reset of the wake-up request signal on pin RXD
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LIN 2.0/SAE J2602 transceiver
7.4 Normal mode
In the normal mode the TJA1021 is able to transmit and receive data via the LIN bus line. The receiver detects the data stream at the LIN bus input pin and transfers it via pin RXD to the microcontroller (see Figure 1): HIGH at a recessive level and LOW at a dominant level on the bus. The receiver has a supply voltage related threshold with hysteresis and an integrated filter to suppress bus line noise. The transmit data stream of the protocol controller at the TXD input is converted by the transmitter into a bus signal with optimized slew rate and wave shaping to minimize EME. The LIN bus output pin is pulled HIGH via an internal slave termination resistor. For a master application an external resistor in series with a diode should be connected between pin INH or VBAT on one side and pin LIN on the other side (see Figure 7). Being in the sleep, standby or Power-up mode, the TJA1021 enters normal mode whenever a HIGH level on pin SLP_N is maintained for a time of at least tgotonorm. The TJA1021 switches to sleep mode in case of a LOW-level on pin SLP_N, maintained for a time of at least tgotosleep.
7.5 Wake-up
When VBAT exceeds the power-on reset threshold voltage Vth(POR)H, the TJA1021 enters the power-on mode. Though the TJA1021 is powered-up and INH is HIGH, both the transmitter and receiver are still inactive. If SLP_N = 1 for t > tgotonorm, the TJA1021 enters normal mode. There are three ways to wake-up a TJA1021 which is in sleep mode: 1. Remote wake-up via a dominant bus state 2. Local wake-up via a negative edge at pin WAKE_N 3. Mode change (pin SLP_N is HIGH) from sleep mode to normal mode
7.6 Remote and local wake-up
A falling edge at pin WAKE_N followed by a LOW-level maintained for a certain time period (twake(dom)WAKE_N) results in a local wake-up. The pin WAKE_N provides an internal pull-up towards pin VBAT. In order to prevent EMI issues, it is recommended to connect an unused pin WAKE_N to pin VBAT. A falling edge at pin LIN followed by a LOW-level maintained for a certain time period (tdom(LIN)) and a rising edge at pin LIN respectively (see Figure 5) results in a remote wake-up. It should be noted that the time period tdom(LIN) is measured either in normal mode while TXD is HIGH, or in sleep mode irrespective of the status of pin TXD. After a local or remote wake-up, pin INH is activated (it goes HIGH) and the internal slave termination resistor is switched on. The wake-up request is indicated by a LOW active wake-up request signal on pin RXD to interrupt the microcontroller.
7.7 Wake-up via mode transition
It is also possible to set pin INH HIGH with a mode transition towards normal mode via pin SLP_N. This is useful for applications with a continuously powered microcontroller.
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LIN 2.0/SAE J2602 transceiver
7.8 Wake-up source recognition
The TJA1021 can distinguish between a local wake-up request on pin WAKE_N and a remote wake-up request via a dominant bus state. The wake-up source flag is set in case the wake-up request was a local one. The wake-up source can be read on pin TXD in the standby mode. If an external pull-up resistor on pin TXD to the power supply voltage of the microcontroller has been added, a HIGH-level indicates a remote wake-up request (weak pull-down at pin TXD) and a LOW-level indicates a local wake-up request (strong pull-down at pin TXD; much stronger than the external pull-up resistor). The wake-up request flag (signalled on pin RXD) as well as the wake-up source flag (signalled on pin TXD) are reset immediately after the microcontroller sets pin SLP_N HIGH.
7.9 TXD dominant time-out function
A TXD dominant time-out timer circuit prevents the bus line from being driven to a permanent dominant state (blocking all network communication) if pin TXD is forced permanently LOW by a hardware and/or software application failure. The timer is triggered by a negative edge on pin TXD. If the duration of the LOW-level on pin TXD exceeds the internal timer value (tto(dom)TXD), the transmitter is disabled, driving the bus line into a recessive state. The timer is reset by a positive edge on pin TXD.
7.10 Fail-safe features
Pin TXD provides a pull-down to GND in order to force a predefined level on input pin TXD in case the pin TXD is unsupplied. Pin SLP_N provides a pull-down to GND in order to force the transceiver into sleep mode in case the pin SLP_N is unsupplied. Pin RXD is set floating in case of lost power supply on pin VBAT. The current of the transmitter output stage is limited in order to protect the transmitter against short circuit to pins VBAT or GND. A loss of power (pins VBAT and GND) has no impact on the bus line and the microcontroller. There are no reverse currents from the bus. The LIN transceiver can be disconnected from the power supply without influencing the LIN bus. The output driver at pin LIN is protected against overtemperature conditions. If the junction temperature exceeds the shutdown junction temperature Tj(sd), the thermal protection circuit disables the output driver. The driver is enabled again on TXD = 0, after the junction temperature dropped below Tj(sd) and a recessive level is present at pin TXD. If VBAT drops below Vth(VBATL)L, a protection circuit disables the output driver. The driver is enabled again on TXD = 0, after VBAT > Vth(VBATL)H and a recessive level is present at pin TXD.
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TJA1021
LIN 2.0/SAE J2602 transceiver
LIN recessive
VBAT
0.6VBAT VLIN 0.4VBAT LIN dominant ground sleep mode standby mode
001aae071
tdom(LIN)
Fig 5. Remote wake-up behavior
8. Limiting values
Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages are referenced to pin GND; unless otherwise specified. Symbol VBAT VTXD VRXD VSLP_N VLIN Parameter supply voltage on pin VBAT voltage on pin TXD voltage on pin RXD voltage on pin SLP_N voltage on pin LIN with respect to GND, VBAT and VWAKE_N only relevant if VWAKE_N < VGND - 0.3 V; current will flow into pin GND Conditions with respect to GND Min -0.3 -0.3 -0.3 -0.3 -40 Max +40 +7 +7 +7 +40 Unit V V V V V
VWAKE_N IWAKE_N
voltage on pin WAKE_N current on pin WAKE_N
-0.3 -15
+40 -
V mA
VINH IO(INH) Tvj Tstg Vesd
voltage on pin INH output current on pin INH virtual junction temperature storage temperature electrostatic discharge voltage according to IEC 61000-4-2 human body model on pins WAKE_N, LIN, VBAT and INH on pins RXD, SLP_N and TXD machine model all pins
[2] [1]
-0.3 -50 -40 -55
VBAT + 0.3 +15 +150 +150
V mA C C
-8 -2 -200
+8 +2 +200
kV kV kV V
[3]
[3]
[4]
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TJA1021
LIN 2.0/SAE J2602 transceiver
[1]
Junction temperature in accordance with IEC 60747-1. An alternative definition is: Tvj = Tamb + P x Rth(vj-a), where Rth(vj-a) is a fixed value. The rating for Tvj limits the allowable combinations of power dissipation (P) and ambient temperature (Tamb). Equivalent to discharging a 150 pF capacitor through a 330 resistor. ESD performance of 6 kV for pins LIN, VBAT and WAKE_N is verified by an external test house. Equivalent to discharging a 100 pF capacitor through a 1.5 k resistor. Equivalent to discharging a 200 pF capacitor through a 10 resistor and a 0.75 H coil.
[2] [3] [4]
9. Thermal characteristics
Table 7. Thermal characteristics According to IEC 60747-1. Symbol Rth(j-a) Rth(j-s) Parameter thermal resistance from junction to ambient thermal resistance from junction to substrate Conditions in free air in free air Typ Unit K/W K/W
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LIN 2.0/SAE J2602 transceiver
10. Static characteristics
Table 8. Static characteristics VBAT = 5.5 V to 27 V; Tvj = -40 C to +150 C; RL(LIN-VBAT) = 500 ; all voltages are defined with respect to ground; positive currents flow into the IC; typical values are given at VBAT = 12 V; unless otherwise specified.[1] Symbol Supply IBAT supply current on pin VBAT sleep mode (VLIN = VBAT; VWAKE_N = VBAT; VTXD = 0 V; VSLP_N = 0 V) standby mode; bus recessive (VINH = VBAT; VLIN = VBAT; VWAKE_N = VBAT; VTXD = 0 V; VSLP_N = 0 V) standby mode; bus dominant (VBAT = 12 V; VINH = 12 V; VLIN = 0 V; VWAKE_N = 12 V; VTXD = 0 V; VSLP_N = 0 V) normal mode; bus recessive (VINH = VBAT; VLIN = VBAT; VWAKE_N = VBAT; VTXD = 5 V; VSLP_N = 5 V) normal mode; bus dominant (VBAT = 12 V; VINH = 12 V; VWAKE_N = 12 V; VTXD = 0 V; VSLP_N = 5 V) Power-on reset Vth(POR)L Vth(POR)H Vhys(POR) Vth(VBATL)L Vth(VBATL)H Vhys(VBATL) LOW-level power-on reset threshold voltage HIGH-level power-on reset threshold voltage power-on reset hysteresis voltage LOW-level VBAT LOW threshold voltage HIGH-level VBAT LOW threshold voltage VBAT LOW hysteresis voltage power-on reset 1.6 2.3 0.05 3.9 4.3 0.15 3.1 3.4 0.3 4.4 4.7 0.3 3.9 4.3 1 4.7 4.9 0.6 V V V V V V 4 7 10 A Parameter Conditions Min Typ Max Unit
150
450
1000
A
300
800
1600
A
400
800
2000
A
1
2
6
mA
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LIN 2.0/SAE J2602 transceiver
Table 8. Static characteristics ...continued VBAT = 5.5 V to 27 V; Tvj = -40 C to +150 C; RL(LIN-VBAT) = 500 ; all voltages are defined with respect to ground; positive currents flow into the IC; typical values are given at VBAT = 12 V; unless otherwise specified.[1] Symbol Pin TXD VIH VIL Vhys RPD(TXD) IIL IOL HIGH-level input voltage LOW-level input voltage hysteresis voltage pull-down resistance on pin TXD LOW-level input current VTXD = 5 V VTXD = 0 V standby mode; VWAKE_N = 0 V; VLIN = VBAT; VTXD = 0.4 V Pin SLP_N VIH VIL Vhys RPD(SLP_N) IIL IOL HIGH-level input voltage LOW-level input voltage hysteresis voltage pull-down resistance on pin SLP_N LOW-level input current VSLP_N = 5 V VSLP_N = 0 V 2 -0.3 0.15 150 -5 1.5 350 0 7 +0.8 0.5 650 +5 V V V k A mA 2 -0.3 50 150 -5 1.5 150 350 7 +0.8 350 650 +5 V V mV k A mA Parameter Conditions Min Typ Max Unit
LOW-level output current local wake-up request;
Pin RXD (open-drain) LOW-level output current normal mode; VLIN = 0 V; VRXD = 0.4 V HIGH-level leakage current HIGH-level input voltage LOW-level input voltage LOW-level pull-up current HIGH-level leakage current switch-on resistance between pins VBAT and INH HIGH-level leakage current VWAKE_N = 0 V VWAKE_N = 27 V; VBAT = 27 V standby; normal mode; power-on mode; IINH = -15 mA; VBAT = 12 V sleep mode; VINH = 27 V; VBAT = 27 V VBAT = 18 V; VLIN = 18 V; VTXD = 0 V normal mode; VLIN = VBAT; VRXD = 5 V
ILH Pin WAKE_N VIH VIL Ipu(L) ILH Pin INH Rsw(VBAT-INH)
-5
0
+5
A
VBAT - 1 -30 -5
-12 0
VBAT + 0.3 VBAT - 3.3 -1 +5
V V A A
-
20
50
ILH
-5
0
+5
A
Pin LIN IBUS_LIM Rpu
TJA1021_1
current limitation for driver dominant state pull-up resistance
40 50
160
100 250
mA k
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LIN 2.0/SAE J2602 transceiver
Table 8. Static characteristics ...continued VBAT = 5.5 V to 27 V; Tvj = -40 C to +150 C; RL(LIN-VBAT) = 500 ; all voltages are defined with respect to ground; positive currents flow into the IC; typical values are given at VBAT = 12 V; unless otherwise specified.[1] Symbol ILH VLIN Parameter HIGH-level leakage current voltage drop on pin LIN Conditions VLIN = 27 V; VBAT = 5.5 V forward, across diode and Rslave; VTXD = 5 V; ILIN = -10 A; standby mode, normal mode and power-on mode VBAT = 27 V; VLIN = 0 V VBAT = 0 V; VLIN = 27 V Min VBAT - 1.2 Typ Max 1 VBAT + 0.4 Unit A V
IL(log) IL(lob) Vth(dom)RX Vth(rec)RX Vth(RX)AV Vth(hys)RX Rslave
loss of ground leakage current loss of battery leakage current receiver dominant threshold voltage receiver recessive threshold voltage average receiver threshold voltage receiver hysteresis threshold voltage slave resistance
-750 0.6VBAT
0.5VBAT 30
+10 1 0.4VBAT 0.525VBAT 0.175VBAT 47
A A V V V V k
Vth(RX)AV = (Vth(rec)RX + Vth(dom)RX) / 2 Vth(hys)RX = Vth(rec)RX - Vth(dom)RX connected between pins LIN and VBAT; VLIN = 0 V; VBAT = 12 V
0.475VBAT 20
Thermal shutdown Tj(sd) shutdown junction temperature 170 C
[1]
All parameters are guaranteed over the virtual junction temperature range by design. Products are 100 % tested at 125 C ambient temperature on wafer level (pre-testing). Cased products are 100 % tested at 25 C ambient temperature (final testing). Both pre-testing and final testing use correlated test conditions to cover the specified temperature and power supply voltage range.
11. Dynamic characteristics
Table 9. Dynamic characteristics VBAT = 5.5 V to 27 V; Tvj = -40 C to +150 C; RL(LIN-VBAT) = 500 ; all voltages are defined with respect to ground; positive currents flow into the IC; typical values are given at VBAT = 12 V; see Figure 6; unless otherwise specified.[1] Symbol Duty cycles 1 duty cycle 1 Vth(rec)(max) = 0.744 x VBAT; Vth(dom)(max) = 0.581 x VBAT; tbit = 50 s; VBAT = 7 V to 18 V Vth(rec)(min) = 0.422 x VBAT; Vth(dom)(min) = 0.284 x VBAT; tbit = 50 s; VBAT = 7.6 V to 18 V
[2][3][4]
Parameter
Conditions
Min 0.396
Typ -
Max -
Unit
2
duty cycle 2
[2][4][5]
-
-
0.581
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LIN 2.0/SAE J2602 transceiver
Table 9. Dynamic characteristics ...continued VBAT = 5.5 V to 27 V; Tvj = -40 C to +150 C; RL(LIN-VBAT) = 500 ; all voltages are defined with respect to ground; positive currents flow into the IC; typical values are given at VBAT = 12 V; see Figure 6; unless otherwise specified.[1] Symbol 3 Parameter duty cycle 3 Conditions Vth(rec)(max) = 0.778 x VBAT; Vth(dom)(max) = 0.616 x VBAT; tbit = 96 s; VBAT = 7 V to 18 V Vth(rec)(min) = 0.389 x VBAT; Vth(dom)(min) = 0.251 x VBAT; tbit = 96 s; VBAT = 7.6 V to 18 V
[3][4]
Min 0.417
Typ -
Max -
Unit
4
duty cycle 4
[4][5]
-
-
0.590
Timing characteristics tf tr t(r-f) tPD(TX) tPD(TX)sym tPD(RX) tPD(RX)sym twake(dom)LIN twake(dom)WAKE_N tgotonorm fall time rise time difference between rise and fall time transmitter propagation delay transmitter propagation delay symmetry receiver propagation delay receiver propagation delay symmetry dominant wake-up time on pin LIN dominant wake-up time on pin WAKE_N go to normal time sleep mode sleep mode time period for mode change from sleep, power-on or standby mode into normal mode
[6] [4] [4] [4]
-4 -2 -2 30 7 2
80 30 5
22.5 22.5 +4 4 +2 6 +2 150 50 10
s s s s s s s s s s
[2]
[6]
tinit(norm) tgotosleep
normal mode initialization time go to sleep time time period for mode change from normal slope mode into sleep mode VTXD = 0 V
2
5
10
s s
tto(dom)TXD
TXD dominant time-out time
27
55
70
ms
[1]
All parameters are guaranteed over the virtual junction temperature range by design. Products are 100 % tested at 125 C ambient temperature on wafer level (pre-testing). Cased products are 100 % tested at 25 C ambient temperature (final testing). Both pre-testing and final testing use correlated test conditions to cover the specified temperature and power supply voltage range. Not applicable for the /10 version of the TJA1021.
[2] [3]
t bus ( rec ) ( min ) 1, 3 = ------------------------------2 x t bit
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[4] [5] [6]
Bus load conditions are: CL = 1 nF and RL = 1 k; CL = 6.8 nF and RL = 660 ; CL = 10 nF and RL = 500 .
t bus ( rec ) ( max 2, 4 = -------------------------------) 2 x t bit
Load condition pin RXD: CRXD = 20 pF and RRXD = 2.4 k.
tbit VTXD
tbit
tbit
tbus(dom)(max) VBAT
tbus(rec)(min)
Vth(rec)(max) LIN BUS signal Vth(dom)(max) Vth(rec)(min) Vth(dom)(min)
thresholds of receiving node 1
thresholds of receiving node 2
tbus(dom)(min) receiving node 1 VRXD
tbus(rec)(max)
tp(rx1)f receiving node 2 VRXD
tp(rx1)r
tp(rx2)r
tp(rx2)f
001aae072
Fig 6. Timing diagram LIN transceiver
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12. Application information
ECU BATTERY LIN BUS LINE
+5 V/ +3.3 V
only for master node
INH VDD RX0 RXD 1 8 7
VBAT 3 WAKE_N
1 k
MICROTX0 CONTROLLER GND Px.x
TXD
4
TJA1021
6 LIN
(1)
SLP_N
2
5
001aae070
More information is available in a separate application note. (1) Master: C = 1 nF; slave: C = 220 pF.
Fig 7. Typical application of the TJA1021
13. Test information
VBAT WAKE_N SLP_N TXD RXD
RRXD CRXD
INH
100 nF RL
TJA1021
LIN GND
CL
001aae069
Fig 8. Test circuit for AC characteristics
Immunity against automotive transients (malfunction and damage) in accordance with LIN EMC Test Specification / Version 1.0; August 1, 2004.
13.1 Quality information
This product has been qualified to the appropriate Automotive Electronics Council (AEC) standard Q100 or Q101 and is suitable for use in automotive critical applications.
TJA1021_1
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LIN 2.0/SAE J2602 transceiver
14. Package outline
SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
D
E
A X
c y HE vMA
Z 8 5
Q A2 A1 pin 1 index Lp 1 e bp 4 wM L detail X (A 3) A
0
2.5 scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT96-1 REFERENCES IEC 076E03 JEDEC MS-012 JEITA EUROPEAN PROJECTION A max. 1.75 0.069 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 5.0 4.8 0.20 0.19 E (2) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z (1) 0.7 0.3 0.028 0.012
0.010 0.057 0.004 0.049
0.019 0.0100 0.014 0.0075
0.244 0.039 0.028 0.041 0.228 0.016 0.024
8o o 0
ISSUE DATE 99-12-27 03-02-18
Fig 9. Package outline SOT96-1 (SO8)
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15. Handling information
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be completely safe you must take normal precautions appropriate to handling integrated circuits.
16. Soldering
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
16.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
16.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus PbSn soldering
16.3 Wave soldering
Key characteristics in wave soldering are:
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LIN 2.0/SAE J2602 transceiver
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities 16.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 10) than a PbSn process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 10 and 11
Table 10. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 11. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 10.
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temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 10. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
17. Revision history
Table 12. TJA1021_1 Revision history Release date 20061016 Data sheet status Objective data sheet Change notice Supersedes Document ID
TJA1021_1
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18. Legal information
18.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
18.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Bare die -- All die are tested on compliance with all related technical specifications as stated in this data sheet up to the point of wafer sawing for a period of ninety (90) days from the date of delivery by NXP Semiconductors. If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There are no post-packing tests performed on individual die or wafers. NXP Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. Accordingly, NXP Semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. It is the responsibility of the customer to test and qualify their application in which the die is used. All die sales are conditioned upon and subject to the customer entering into a written die sale agreement with NXP Semiconductors through its legal department.
18.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
18.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
19. Contact information
For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com
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20. Contents
1 2 2.1 2.2 2.3 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 8 9 10 11 12 13 13.1 14 15 16 16.1 16.2 16.3 16.4 17 18 18.1 18.2 18.3 18.4 19 20 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Low power management . . . . . . . . . . . . . . . . . 1 Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Operating modes . . . . . . . . . . . . . . . . . . . . . . . 5 Sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Remote and local wake-up . . . . . . . . . . . . . . . . 7 Wake-up via mode transition . . . . . . . . . . . . . . 7 Wake-up source recognition . . . . . . . . . . . . . . . 8 TXD dominant time-out function . . . . . . . . . . . . 8 Fail-safe features . . . . . . . . . . . . . . . . . . . . . . . 8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 9 Thermal characteristics. . . . . . . . . . . . . . . . . . 10 Static characteristics. . . . . . . . . . . . . . . . . . . . 11 Dynamic characteristics . . . . . . . . . . . . . . . . . 13 Application information. . . . . . . . . . . . . . . . . . 16 Test information . . . . . . . . . . . . . . . . . . . . . . . . 16 Quality information . . . . . . . . . . . . . . . . . . . . . 16 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 17 Handling information. . . . . . . . . . . . . . . . . . . . 18 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Introduction to soldering . . . . . . . . . . . . . . . . . 18 Wave and reflow soldering . . . . . . . . . . . . . . . 18 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 18 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 19 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 20 Legal information. . . . . . . . . . . . . . . . . . . . . . . 21 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 21 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Contact information. . . . . . . . . . . . . . . . . . . . . 21 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2006.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 16 October 2006 Document identifier: TJA1021_1
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